7 Revision History¶
7.1 Firmware¶
- 1.24120 — 2024-04-30
- Improved ADC/TDC synchronisationAdded sample averaging modes AA/DD, AAAA/DDDD, and AADDTiGer UpdatesInternal optimizationsBug fixes
- 5493 — 2023-10-30
- Fixed bug related to level triggeringFixed first packet being emptyMinor bug fixes
- 5467 — 2023-05-05
- PCIe optimizationsMinor bug fixes
7.2 Driver¶
- 2.0.1 — 2024-07-17
- Extensive revision of the application programming interfaceImproved linux supportImproved documentationImproved TDC and ADC synchronisation
- 1.5.4 — 2024-07-13
- Fixed 2 channel handling with trigger from opposite channel (trigger A on channel D)Fixed timestamp uncertainty in lower bits
- 1.5.3 — 2024-07-07
- Dynamic reconfiguration with .cronorom support
- 1.4.5 — 2023-01-23
- Crono kernel driver update to v1.4.2Added support for revision 3 boardsMinor bug fixesSupport for 32-bit OS discontinued
- 1.4.0 — 2022-08-18
- Added support for external 10 MHz reference on slot bracket
- 1.3.0 — 2022-05-25
- Added support for Averager
7.3 User Guide¶
- 1.0.1 — 2024-10-22
- Improved Figure 1.1
- 1.0.0 — 2024-10-17
- Added digitizer characteristicsAdded chapter on TiGerAdded ErratumFixed gating documentationMany corrections
- 0.2.1 — 2024-10-01
- Corrections in Export Control
- 0.2.0 — 2024-10-01
- Added gating examplesUpdated Export Control
- 0.1.4 — 2024-08-06
- Added figures for the Trigger Matrix and Gating Blocks.
- 0.1.3 — 2024-08-01
- Added documentation for clock connectionsAdded link to current user guide example codeRemoved clutter from the APIs “ON THIS PAGE” sidebarUpdated C++ exampleGeneral improvements
- 0.1.2 — 2024-07-17
- Renamed FPGA0/1 to TRG/GATERestructured API documentationExpanded documentation on Packet Format
- 0.1.1 — 2024-07-16
- Corrected values in introductionImproved phrasing throughout
- 0.1.0 — 2024-07-11
- Initial release