2.1 ADC Modes

The ADC quantizes the input signal using 12 bits. By default, these are mapped to signed 16 bit (for more details, see Section 4.4).

Data processing such as trigger detection or packet building are always performed at 5 ns intervals. Depending on the ADC mode, this interval may contain 32 (1-Channel Mode @ 6.4 Gsps), 16 (2-Channel Mode @ 3.2 Gsps) or 8 (4-Channel Mode @ 1.6 Gsps) samples.

The ADC mode is configured using ndigo6g12_configuration::adc_mode.

The board supports using one, two or four channels.

During interleaving, the Ndigo6G-12 firmware reorders and groups the data into a linear sample stream. The process is fully transparent. For users, the only difference is that a 5 ns cycle can contain 8, 16 or 32 samples, depending on the mode.

2.1.1 1-Channel Modes A and D

In these modes, only a single channel is used. The analog signal on that channel is digitized at 6.4 Gsps. Packet size is always a multiple of 32 samples per 5 ns (See Figures 2.1 and 2.12).

For this mode, ndigo6g12_static_info::application_type needs to be either NDIGO6G12_APP_TYPE_1CH or NDIGO6G12_APP_TYPE_AVRG.

Figure 2.1: ADCs in 1-channel-mode A, B, C or D interleaved for 6.4 Gsps.

2.1.2 2-Channel Mode AD

In this mode, two channels are used simultaneously. The analog signals on these channels are digitized at 3.2 Gsps each. Packet size is always a multiple of 16 samples per 5 ns (See Figures 2.2 and 2.11).

For this mode, ndigo6g12_static_info::application_type needs to be NDIGO6G12_APP_TYPE_2CH.

Figure 2.2: ADCs in 2-channel-mode AD, interleaved for 3.2 Gsps.

2.1.3 4-Channel Mode ABCD

In this mode, all four channels are digitized independently at 1.6 Gsps each. The packet size is always a multiple of 16 samples per 10 ns. (See Figures 2.3 and 2.10).

For this mode, ndigo6g12_static_info::application_type needs to be NDIGO6G12_APP_TYPE_4CH.

Figure 2.3: ADCs in 4-channel-mode ABCD at 1.6 Gsps.

2.1.4 Multiple Sampling Modes

In these modes, only the specified input channels are used, but the channels are sampled independently by the ADC cores. The output of the board depends on ndigo6g12_configuration::sample_averaging.

• sample_averaging == false: The digitized samples are output as separate packets (the number of which depends on the selected mode).

• sample_averaging == true: The average of the digitized samples is calculated and output as one single packet.

Using the same trigger settings on all ADCs can be used to reduce noise by averaging the four channels. To deal with complex triggering conditions, different trigger settings on each of the ADCs can be used.

The Ndigo6G-12 provides four ADCs sampling at 1.6 Gsps each. Higher speed modes are implemented by interleaving two or four of these ADCs.

Modes AA and DD

In this mode, input channel A (or D) is sampled at 3.2 Gsps two times and independently by the internal ADC cores, see Figure 2.4.

For this mode, ndigo6g12_static_info::application_type needs to be NDIGO6G12_APP_TYPE_2CH.

Figure 2.4: ADCs in 2-channel-mode AA or DD at 3.2 Gsps.

Mode AADD

In this mode, input channel A and D are sampled at 1.6 Gsps two times and independently by the internal ADC cores, see Figure 2.5.

For this mode, ndigo6g12_static_info::application_type needs to be NDIGO6G12_APP_TYPE_4CH.

Figure 2.5: ADCs in 4-channel-mode AADD at 1.6 Gsps.

Modes AAAA, DDDD

In this mode, input channel A (or D) are sampled at 1.6 Gsps four times and independently by the internal ADC cores, see Figure 2.6.

For this mode, ndigo6g12_static_info::application_type needs to be NDIGO6G12_APP_TYPE_4CH.

Figure 2.6: ADCs in 4-channel-mode AAAA or DDDD at 1.6 Gsps.