3.4 Configuration¶

The Ndigo6G-12 board is configured with a configuration structure (ndigo6g12_configuration).

The user should first obtain a standard set of configuration parameters using ndigo6g12_get_default_configuration(), then modify only the necessary parameters to their specific needs.

The configuration itself is done by calling ndigo6g12_configure().

int ndigo6g12_get_default_configuration(ndigo6g12_device *device, ndigo6g12_configuration *config)¶

Copies the default configuration to the specified config pointer.

Default values of ndigo6g12_configuration:

adc_mode =
- NDIGO6G12_ADC_MODE_A (if application_type = NDIGO6G12_APP_TYPE_1CH)
- NDIGO6G12_ADC_MODE_AD (if application_type = NDIGO6G12_APP_TYPE_2CH)
- NDIGO6G12_ADC_MODE_ABCD (if application_type = NDIGO6G12_APP_TYPE_4CH)
- NDIGO6G12_ADC_MODE_A (if application_type = NDIGO6G12_APP_TYPE_AVRG)
adc_cal_set = 3
analog_offsets[i] = 0
tdc_trigger_offsets[i] = NDIGO6G12_DC_OFFSET_N_NIM
trigger[i]:
- edge = true
- rising = false
- threshold = 512
trigger_block[i]:
- enabled = false
- retrigger = false
- multi_shot_count = 1
- precursor = 0
- length = 16
- sources = NDIGO6G12_TRIGGER_SOURCE_<channel>0
- gates = NDIGO6G12_TRIGGER_GATE_NONE
- minimum_free_packets = 0
gating_block[i]:
- negate = false
- retrigger = false
- start = 0
- stop = 1000
- sources = NDIGO6G12_TRIGGER_SOURCE_<channel>0
tdc_configuration:
- channel[i]:
  - enable = false
  - gating_block:
    - enable = false
    - negate = false
    - retrigger = false
    - retrigger = NDIGO6G12_TRIGGER_SOURCE_AUTO
    - start = 0
    - stop = 1000
    - sources = NDIGO6G12_TRIGGER_SOURCE_<channel>0
  - tiger_block:
    - mode = NDIGO6G12_TIGER_OFF
    - negate = true
    - retrigger = false
    - retrigger = NDIGO6G12_TRIGGER_SOURCE_AUTO
    - start = 0
    - stop = 1
    - sources = NDIGO6G12_TRIGGER_SOURCE_<channel>0
- skip_alignment = false
- alignment_mode = false
- alignment_pin_high_z = false
- alignment_pin_invert = false
- alignment_phase_steps = 6
- send_empty_packets = false
auto_trigger_period = 200000
auto_trigger_random_exponent = 0
output_mode =
- NDIGO6G12_OUTPUT_MODE_SIGNED32 (if application_type = NDIGO6G12_APP_TYPE_AVRG)
- NDIGO6G12_OUTPUT_MODE_SIGNED16 (otherwise)
extended_bandwidth = false
ramp_test_mode = false

Parameters:

device – [in] Pointer to the device from which to get the information.
config – [out] Pointer to a structure in which to store the configuration values.

Returns:

See Function return values.

int ndigo6g12_configure(ndigo6g12_device *device, ndigo6g12_configuration *config)¶

Configures the Ndigo6G-12 device.

The config information is copied such that it can be changed after the call to ndigo6g12_configure.

Parameters:

device – [in] Pointer to the device from which to get the information.
config – [out] Pointer to the configuration structure.

Returns:

See Function return values.

struct ndigo6g12_configuration¶

Structure that contains the configuration values for the Ndigo6G-12.

This structure contains the configuration information. It is used in conjunction with ndigo6g12_get_default_configuration() and ndigo6g12_configure().

Public Members

int adc_mode¶

Configure ADC mode.

The chosen ADC mode has to be supported by the current NDIGO6G12_APP_TYPE.

For example, if NDIGO6G12_APP_TYPE_1CH is used, one cannot choose, e.g., adc_mode = NDIGO6G12_ADC_MODE_AA, but one has to either choose NDIGO6G12_ADC_MODE_A or NDIGO6G12_ADC_MODE_D.

Default value depends on ndigo6g12_init_parameters::application_type.

For more information, see Section 2.1.

Must be one of the following:

NDIGO6G12_ADC_MODE_ABCD¶: 4-channel mode at 1600 Msps sample rate

NDIGO6G12_ADC_MODE_AADD¶: 4-channel mode at 1600 Msps sample rate

NDIGO6G12_ADC_MODE_AAAA¶: 4-channel mode at 1600 Msps sample rate

NDIGO6G12_ADC_MODE_DDDD¶: 4-channel mode at 1600 Msps sample rate

NDIGO6G12_ADC_MODE_AD¶: 2-channel mode at 3200 Msps sample rate

NDIGO6G12_ADC_MODE_AA¶: 2-channel mode at 3200 Msps sample rate

NDIGO6G12_ADC_MODE_DD¶: 2-channel mode at 3200 Msps sample rate

NDIGO6G12_ADC_MODE_A¶: 1-channel mode at 6400 Msps sample rate

NDIGO6G12_ADC_MODE_D¶: 1-channel mode at 6400 Msps sample rate

int adc_cal_set¶

Select ADC calibration set.

Default is 3. Do not change.

double analog_offsets[NDIGO6G12_ADC_CHANNEL_COUNT]¶

Set the offsets of the ADC inputs in V.

The indices 0 to 3 of the array correspond to ADC channels A to D.

Must be between \(\pm\) 0.5 V.

Defaults are 0 V for each ADC channel.

double tdc_trigger_offsets[NDIGO6G12_TDC_CHANNEL_COUNT]¶

Set DAC for trigger threshold of the TDC inputs in V.

Channel assignment:

0 to 3: high-resolution TDC, inputs E to H
4 and 5: inputs TRG and GATE

Set to a value between −1.32 V and +2.0 V.

This should be close to 50% of the height of your pulses on the inputs. Examples for various signaling standards are defined below. The inputs are AC coupled. This means that for pulse inputs the absolute voltage is not important. Only the relative pulse amplitude causes the input circuits to switch. tdc_trigger_offset for an input must be set to the relative switching voltage for the input standard in use. If the pulses are negative, a negative switching threshold must be set and vice versa.

Defaults are NDIGO6G12_DC_OFFSET_N_NIM for each TDC channel.

Defines for various signal standards:

NDIGO6G12_DC_OFFSET_P_NIM¶

NDIGO6G12_DC_OFFSET_P_CMOS¶

NDIGO6G12_DC_OFFSET_P_LVCMOS_33¶

NDIGO6G12_DC_OFFSET_P_LVCMOS_25¶

NDIGO6G12_DC_OFFSET_P_LVCMOS_18¶

NDIGO6G12_DC_OFFSET_P_TTL¶

NDIGO6G12_DC_OFFSET_P_LVTTL_33¶

NDIGO6G12_DC_OFFSET_P_LVTTL_25¶

NDIGO6G12_DC_OFFSET_P_SSTL_3¶

NDIGO6G12_DC_OFFSET_P_SSTL_2¶

NDIGO6G12_DC_OFFSET_N_NIM¶

NDIGO6G12_DC_OFFSET_N_CMOS¶

NDIGO6G12_DC_OFFSET_N_LVCMOS_33¶

NDIGO6G12_DC_OFFSET_N_LVCMOS_25¶

NDIGO6G12_DC_OFFSET_N_LVCMOS_18¶

NDIGO6G12_DC_OFFSET_N_TTL¶

NDIGO6G12_DC_OFFSET_N_LVTTL_33¶

NDIGO6G12_DC_OFFSET_N_LVTTL_25¶

NDIGO6G12_DC_OFFSET_N_SSTL_3¶

NDIGO6G12_DC_OFFSET_N_SSTL_2¶

ndigo6g12_trigger trigger[NDIGO6G12_TRIGGER_COUNT]¶

Configuration of the external trigger sources.

The entries in the array correspond to the following defines.

ndigo6g12_trigger::threshold is ignored for index NDIGO6G12_TRIGGER_TDC0 and above.

ndigo6g12_trigger::edge and ndigo6g12_trigger::rising are ignored for indeces NDIGO6G12_TRIGGER_AUTO and NDIGO6G12_TRIGGER_ONE.

NDIGO6G12_TRIGGER_A0¶

NDIGO6G12_TRIGGER_A1¶

NDIGO6G12_TRIGGER_B0¶

NDIGO6G12_TRIGGER_B1¶

NDIGO6G12_TRIGGER_C0¶

NDIGO6G12_TRIGGER_C1¶

NDIGO6G12_TRIGGER_D0¶

NDIGO6G12_TRIGGER_D1¶

NDIGO6G12_TRIGGER_TDC0¶

NDIGO6G12_TRIGGER_TDC1¶

NDIGO6G12_TRIGGER_TDC2¶

NDIGO6G12_TRIGGER_TDC3¶

NDIGO6G12_TRIGGER_TRG¶

NDIGO6G12_TRIGGER_GATE¶

NDIGO6G12_TRIGGER_AUTO¶

NDIGO6G12_TRIGGER_ONE¶

NDIGO6G12_TRIGGER_FPGA0¶: Deprecated. Alias for NDIGO6G12_TRIGGER_TRG.

NDIGO6G12_TRIGGER_FPGA1¶: Deprecated. Alias for NDIGO6G12_TRIGGER_GATE.

ndigo6g12_trigger_block trigger_block[NDIGO6G12_ADC_CHANNEL_COUNT]¶

Trigger settings of ADC inputs.

The number of input channels depends on ADC mode.

ndigo6g12_gating_block gating_block[NDIGO6G12_GATE_COUNT]¶

Configuration of gating blocks.

Gating blocks are used to filter trigger.

ndigo6g12_tdc_configuration tdc_configuration¶: Configuration of TDC channels.

ndigo6g12_averager_configuration average_configuration¶: Configuration of the Averager.

int auto_trigger_period¶

Component to create a trigger either periodically or randomly.

To be exact, there are two parameters \(M\) = auto_trigger_period and \(N\) = auto_trigger_random_exponent that result in a distance between triggers of \( T = M + [1 \dots 2^N] - 1 \) clock cycles, where \( 6 \le M < 2^{32} \) and \( 0 \le N < 32 \).

There is no enable or reset as the usage of this trigger can be configured in the channels. Each clock cycle is 5 ns.

Default is 200000, corresponding to a 1 kHz auto trigger.

int auto_trigger_random_exponent¶

Component to create a trigger either periodically or randomly.

See auto_trigger_period.

Default is 0.

int output_mode¶

Output mode of the ADC data.

Default value depends on ndigo6g12_init_parameters::application_type.

NDIGO6G12_APP_TYPE_AVRG: NDIGO6G12_OUTPUT_MODE_SIGNED32
otherwise: NDIGO6G12_OUTPUT_MODE_SIGNED16.

Must be one of the following:

NDIGO6G12_OUTPUT_MODE_RAW¶

Return the native range (0 to 4095).

Not supported for user applications.

NDIGO6G12_OUTPUT_MODE_SIGNED16¶

Return a signed16 integer.

The range is −32768 to 32767.

NDIGO6G12_OUTPUT_MODE_SIGNED32¶

Output in signed32 integer format.

Must be used in (and only in) averaging mode. The range is −2³¹ to 2³¹ − 1.

For more information, see Section 4.4.

crono_bool_t extended_bandwidth¶

Extended bandwidth.

If true, the input bandwidth is 6.5 GHz instead of the default 4.5 GHz.

Since the extended input bandwidth of the ADC influences the total bandwidth of the Ndigo6G-12 board only in a minimal manner, we recommend using the non-extended input bandwidth of 4.5 GHz. This ensures the best signal-to-noise ratio.

Default is false.

crono_bool_t ramp_test_mode¶: Default is false. Do not change.

crono_bool_t sample_averaging¶

Calculate sample average for multi-sampling modes AAAA, DDDD, AADD, AA, and DD.

Manipulate the output in multi-sampling modes.

true: Average all samples and combine them to a single output.
false: Output all samples in their own package.

For more information, see Multiple Sampling Modes in Section 2.1.

struct ndigo6g12_trigger¶

Structure that contains trigger settings.

Public Members

short threshold¶

Threshold controlling when the ADC channel is active.

Sets the threshold for the trigger block within the range of the ADC data. The range depends on ndigo6g12_configuration::output_mode:

NDIGO6G12_OUTPUT_MODE_RAW : 0 to 4096
NDIGO6G12_OUTPUT_MODE_SIGNED16 : −32768 to 32767

For trigger indices NDIGO6G12_TRIGGER_TDC to NDIGO6G12_TRIGGER_ONE the threshold is ignored.

For the TDC channels, the trigger threshold is controlled by ndigo6g12_configuration::tdc_trigger_offsets.

crono_bool_t edge¶

Enables edge-trigger functionality.

For trigger indices NDIGO6G12_TRIGGER_AUTO and NDIGO6G12_TRIGGER_ONE this is ignored.

false: Use a level trigger. The level trigger triggers as long as the signal is above or below (depending on rising) the set threshold. Followingly, the trigger gives the sign of the signal in reference to the threshold.
true: Use an edge trigger. The edge trigger triggers as soon as its set threshold is crossed by the signal. Thus, the roots in reference to the threshold are recorded.

Default is true.

crono_bool_t rising¶

Sets rising-edge trigger functionality.

For trigger indices NDIGO6G12_TRIGGER_AUTO and NDIGO6G12_TRIGGER_ONE, this is ignored.

If edge is true (i.e., an edge trigger is used):
- false: Trigger when the signal crosses from above to below the threshold.
- true: Trigger when the signal crosses from below to above the threshold.
If edge is false (i.e., a level trigger is used):
- false: Triggers the part of the signal below the threshold.
- true: Triggers the part of the signal above the threshold.

Default is false.

struct ndigo6g12_trigger_block¶

Configuration of the trigger block.

Public Members

crono_bool_t enabled¶: Activates triggers on this channel.

crono_bool_t retrigger¶

Enable retrigger functionality.

If a new trigger condition occurs while the postcursor is acquired (i.e., within the time frame controlled by length), the packet is extended by starting a new postcursor. Otherwise the new trigger is ignored and the packet ends after the postcursor of the first trigger.

int multi_shot_count¶

Number of packets created in single-shot mode (i.e., ndigo6g12_single_shot() was called) before packet generation stops.

This value is ignored if enabled is true.

Maximum is NDIGO6G12_MAX_MULTISHOT.

Note: Up to firmware revision 1.24120, this feature is bugged in 4-channel mode while multi_shot_count > 1.

int precursor¶

Precursor in multiples of 5 ns.

The amount of data preceding a trigger that is captured. The maximum is NDIGO6G12_MAX_PRECURSOR.

int length¶

Length of the postcursor in multiples of 5 ns.

The total amount of data that is recorded in addition to the trigger window is controlled by length and precursor. precursor determines the amount of data before the trigger window, length the amount of data after the trigger condition was false the first time.

In edge-trigger mode , the trigger window is always 1 (i.e., 5 ns long). Otherwise, (level-trigger mode) the trigger window is as long as the trigger condition was fulfilled.

The maximum value is NDIGO6G12_FIFO_DEPTH minus ndigo6g12_trigger_block::precursor minus trigger window.

int sources¶

A bit mask with a bit set for all trigger sources that can trigger this channel.

Default NDIGO6G12_TRIGGER_SOURCE_<channel>0 (NDIGO6G12_TRIGGER_SOURCE_A0 for ADC channel A, NDIGO6G12_TRIGGER_SOURCE_B0 for ADC channel B, etc).

int gates¶

A bit mask with a bit set for all trigger gates.

Mask which selects the gates that have to be open for the trigger block to use.

Default NDIGO6G12_TRIGGER_GATE_NONE.

The following defines can be used to create the bit mask:

NDIGO6G12_TRIGGER_GATE_NONE¶

NDIGO6G12_TRIGGER_GATE_0¶

NDIGO6G12_TRIGGER_GATE_1¶

NDIGO6G12_TRIGGER_GATE_2¶

NDIGO6G12_TRIGGER_GATE_3¶

double minimum_free_packets¶

Number of packets that fit into the FIFO.

This parameter sets how many packets are supposed to fit into the on-board FIFO before a new packet is recorded after the FIFO was full, i.e., a certain amount of free space in the FIFO is demanded before a new packet is written after the FIFO was full. As a measure for the packet length, the recording window as defined by precursor and length is used.

The on-board algorithm checks the free FIFO space only in case the FIFO is full. Therefore, if this number is 1.0 or more, at least every second packet in the host buffer is guaranteed to have the full length set by the precursor and length. In many cases smaller values will also result in full length packets. But below a certain value multiple packets that are cut off at the end will show up.

Default is 0.

struct ndigo6g12_gating_block¶

Contains settings of the gating block.

After a signal at one of the sources is detected, a timer starts running. Once the timer reaches the value specified by start, a gate is opened (or closed, depending on negate) until the timer reaches the time specified by stop.

What happens in the event that another signal before stop is detected is controlled by retrigger.