Trigger Setup

The Ndigo6G-12 records analog waveforms using zero suppression. Whenever a relevant waveform is detected, data is written to an internal FIFO memory.

Each ADC channel has two trigger units. These can be configured independently (e.g., one unit could trigger on rising edges, the other on falling). They are configured with config.trigger.

Each ADC channel has a corresponding trigger block that determines whether data is written to the internal FIFOs. The trigger blocks are configured with config.trigger_block. Each trigger block can take any amount of trigger units as a source (for details, see ndigo6g12_trigger_block::sources or Trigger inputs), thus, enabling sophisticated trigger setups.

Trigger Configuration

Analog Inputs

Users can specify a threshold and can choose whether triggering is used whenever incoming data is below or above the threshold (level triggering, see Figure 15) or only if data exceeds the threshold (edge triggering, see Figure 16).

Figure 15 Example for level triggering.

Figure 16 Example for edge triggering.

A gate length can be set to extend the recording window by multiples of 5 ns. Furthermore, a precursor window can be specified, causing the trigger unit to write data to the FIFO (precursor \(\times\) 5 ns) before the trigger event.

When edge triggering is used, all packets have the same length of (precursor + length + 1)-cycles of 5 ns. For level triggering, packet length is data dependent.

If retrigger is enabled and the trigger conditions are fulfilled during the recording of the postcursor, the recording window is extended (see Figure 14).

Figure 17 Triggering in 4-channel mode at 8 samples per clock cycle.

Figure 18 Triggering in 2-channel mode at 16 samples per clock cycle.

Figure 19 Triggering in 1-channel mode at 32 samples per clock cycle.

Digital Inputs

For all digital inputs, the configuration value ndigo6g12_trigger::threshold is ignored. Their trigger threshold is configured by ndigo6g12_configuration::tdc_trigger_offsets.

Equivalently to the analog inputs, edge- or level-trigger functionality can be enabled using ndigo6g12_trigger::edge. The duration of a level trigger is solely limited by the AC-coupling (see Figure 6 for the effects of AC-coupling on a signal).

Trigger inputs

A trigger_block can use several input sources:

• The eight trigger decision units of all four ADC channels (Figure 20)

• The four TDC and the two digital control inputs (Figure 21)

• A function trigger providing random or periodic triggering (see Auto Triggering Function Generator).

Trigger inputs from the above sources can be concatenated using a logical OR by setting the appropriate bits in the bitmask (see ndigo6g12_trigger_block::sources).

See also Figure 22.

Figure 20 From the ADC inputs, a trigger unit creates an input flag for the trigger matrix. Each digitizer channel (A, B, C, D) has two trigger units.

Figure 21 The digital inputs TDC0, TDC1, TDC2, TDC3, TRG, and GATE have simpler trigger units.

Figure 22 Trigger Matrix. The eight trigger signals from the four analog channels and the trigger signals from the six digital channels (four TDC channels, TRG, GATE) can be combined to create a trigger input for each trigger block. Additionally, four gate signals (see Figure 23) can be used to suppress trigger during configurable time frames.

Gating Trigger Events

Triggers can be fed into the gating_blocks as outlined in Gating Blocks and Figure 23.

In return, the gating_blocks can be used to block writing data to the FIFO. That way, only zero-suppressed data occurring when the selected gate is active is transmitted. This procedure reduces PCIe bus load even further.

Which gating_block is used to block a particular trigger_block is configured with ndigo6g12_trigger_block::gates.